Implantable microelectronic device and method of manufacture

ABSTRACT

An implantable hermetically sealed microelectronic device, and method of manufacture are disclosed. The microelectronic device of the present invention is hermetically encased in a insulator, such as alumina formed by ion bean assisted deposition (“IBAD”), with a stack of biocompatible conductive layers extending from a contact pad on the device to an aperture in the hermetic layer. In a preferred embodiment, one or more patterned titanium layers are formed over the device contact pad, and one or more platinum layers are formed over the titanium layers, such that the top surface of the upper platinum layer defines an external, biocompatible electrical contact for the device. Preferably, the bottom conductive layer is larger than the contact pad on the device, and a layer in the stack defines a shoulder.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority of Provisional Patent Application No.60/732,884, “Implantable Microelectronic Device and Method ofManufacture,” filed Nov. 02, 2005, the disclosure of which isincorporated herein by reference.

FEDERALLY SPONSORED RESEARCH

This invention was made with governmental support under grant No.R24EY12893-01, awarded by the National Institutes of Health. The federalgovernment has certain rights in this invention.

FIELD OF THE INVENTION

The present invention is related to implantable medical devices, and isparticularly related to implantable microelectronic devices.

BACKGROUND OF THE INVENTION

Biocompatibility is a critical concern for medical devices that aredesigned to be implanted in vivo. Biocompatibility is necessary to avoidadverse reactions in the subject, and to avoid device failure as aresult of exposure to the corrosive saline body fluids and othersubstances in the tissue surrounding the implant. Where an implanteddevice includes one or more components that are not, themselves,biocompatible, it is known to provide hermetic sealing of such deviceswith a chemically inert coating to achieve biocompatibility, i.e., inorder to avoid adverse reactions and device degradation. Many suchimplantable devices are intended to remain in place over long periods oftime, imposing a long life requirement on the manner of hermeticsealing.

Miniature implantable medical devices commonly include microelectroniccomponents, such as integrated circuit chips fabricated on siliconsubstrates. Ion beam assisted deposition (“IBAD”) of alumina, oftenreferred to an aluminum oxide (Al₂O₃), has been proposed forhermetically sealing such devices. Alumina has good biocompatibility,and IBAD is a useful technique for depositing dense, adherent,defect-free conformal thin films. The use of IBAD to deposit alumina onimplantable medical devices is described in U.S. Pat. No. 6,844,023,entitled “Alumina Insulation For Coating Implantable Components AndOther Microminiature Devices,” the disclosure of which is incorporatedby reference.

Most implantable microelectronic devices require means for connecting tothe devices for purposes of supplying power to the device or for routingelectrical signals to or from the device. Such devices include, forexample, stimulators which operate by providing current to thesurrounding tissue, and sensors which measure chemical or electricalproperties of the surrounding tissue. When an insulator, such asalumina, is used as a coating on a device to provide hermetic sealing, aconductive path through the alumina to an external contact is typicallyrequired. For implantable devices fabricated on silicon using standardsilicon processing technology, the contact pads on the device arenormally copper or aluminum, neither of which is biocompatible. Thus,semiconductor device contact pads cannot simply be left exposed bypatterning the surrounding alumina layer.

A prior art structure addressing the need to provide means forconnecting to a sealed, implantable electronic device is disclosed inU.S. Pat. No. 6,516,808, entitled “Hermetic Feedthrough For AnImplantable Device,” the disclosure of which is also incorporated byreference. The '808 patent depicts several embodiments of “hermetic”electrical feedthrough structures. Thus, the embodiment of FIGS. 5A and5B of the patent show simple via structures, while the embodiments ofFIGS. 6A, 6B and 7 show “serpentine” feedthrough structure which aresaid to provide greater “hermeticity.” Implicit in the '808 patent'sdiscussion of the serpentine feedthrough structures, and as confirmed bythe inventors hereof, is the fact that the prior art simple viafeedthrough structures are not adequately hermetic, particularly inapplications where they will remain in vivo for a lengthy period. Whileuse of a serpentine structure may overcome this inadequacy, suchstructures are generally more difficult to fabricate and, in someinstances, consume valuable “real estate” on the surface of the device.

Another approach to providing a hermetic electrical path through aconformal electrically insulating film is described in co-assigned U.S.Pat. No. 6,858,220, the disclosure of which is incorporated byreference. The '220 patent describes extremely thin (e.g., 40 nm)ultra-nanocrystalline diamond coatings wherein an electric path throughthe film is created by selective ion implantation. Unfortunately, thissolution has limited applicability to extremely thin films that can berendered suitably conductive by ion implantation.

Accordingly, a structure which provides better hermetic sealing of afeedthrough between an implantable microelectronic device and thesurface of an encapsulating insulator is needed.

SUMMARY OF THE INVENTION

In a first aspect, the present invention is directed to an implantablemicroelectronic device having an electrical contact pad that is made ofa non-biocompatible material; a plurality of thin, biocompatible,patterned conductive layers formed over the electrical contact pad, thetop surface of the patterned conductive layers defining an electricalcontact, and the first conductive layer being in direct contact with theelectrical contact pad; a biocompatible electrically insulating materialhermetically surrounding the device, the electrically insulatingmaterial having an aperture wherein the electrical contact ispositioned. Preferably the electrically insulating material is abiocompatible ceramic, such as alumina, and the patterned conductivelayers comprise one or more platinum layers formed on one or moretitanium layers. The microelectronic device may be an integrated circuitchip, such that the electrical contact pad is aluminum or copper.Preferably, the first patterned conductive layer is larger in itslateral dimensions than the contact pad, such that the layer extendsbeyond the edge of the contact pad, forming a shoulder.

In another aspect the present invention is directed to an implantabledevice, comprising a microelectronic device having a conductive contactpad surrounded by electrically insulating material, at least onepatterned titanium layer formed on the contact pad and extending beyondthe edge of the contact pad, at least one patterned platinum layerformed over the titanium layer, the platinum layer having an exposedupper contact surface, and an alumina layer hermetically surrounding themicroelectronic device and the patterned layers, the alumina layerhaving an aperture which exposes the upper contact surface. Preferably,the device has a plurality of patterned titanium layers and a pluralityof patterned platinum layers, and one of the patterned titanium layerdefines a shoulder.

In another aspect the present invention is directed to a method ofmaking an implantable device having an electrical contact, comprising:(1) providing an electrical device having a contact pad, (2) forming aplurality of biocompatible, patterned conductive layers over the contactpad, the plurality of conductive layers having a first layer formed onthe contact pad and a top electrical contact surface, (3) forming ahermetic, biocompatible electrically insulating layer over the resultingstructure, and (4) forming an aperture in the electrically insulatinglayer to expose the electrical contact surface. Preferably, thehermetic, biocompatible electrically insulating layer is a ceramicmaterial, such as alumina, formed by ion beam assisted deposition.Likewise, preferably the patterned conductive layers are formed by ionbeam assisted deposition of metals, such as titanium and platinum, andat least one patterned conductive layer is larger than the contact padsuch that it extends beyond the edge of the contact pad. In addition,preferably, at least one of the patterned conductive layers has ashoulder. The step of forming an aperture preferably comprises use oflaser machining. A sacrificial layer may optionally be formed over thetop electrical contact surface, such that the top electrical contactsurface is protected during subsequent processing. Thereafter, thesacrificial layer may be removed.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects and the attendant advantages of this inventionwill become more readily apparent by reference to the following detaileddescription when taken in conjunction with the accompanying drawings,wherein:

FIG. 1 is a cross-sectional view of an embodiment of the presentinvention.

FIG. 2A is a cross-sectional view of the embodiment of FIG. 1 at aninterim step during fabrication.

FIG. 2B is a cross-sectional view of the embodiment of FIG. 1 at a laterstep of fabrication.

FIG. 3 is a cross-sectional view of an alternate embodiment of thepresent invention having a built up electrode.

FIG. 4 is a cross-sectional view of an alternate embodiment of thepresent invention showing the mask deposition.

FIG. 5 is a cross-sectional view of an alternate embodiment of thepresent invention showing the mask patterning.

FIG. 6 is a cross-sectional view of an alternate embodiment of thepresent invention showing the material deposition.

FIG. 7 is a cross-sectional view of an alternate embodiment of thepresent invention showing the mask polymer removal.

FIG. 8 shows a flow chart of packaging and patterning of Si Swizzle.

Reference symbols are used in the Figures to indicate certaincomponents, aspects or features shown therein, with reference symbolscommon to more than one Figure indicating like components, aspects orfeatures shown therein. It is noted that none of the figures used todescribe the present invention are drawn to scale, and various featuresand dimensions are greatly exaggerated to facilitate the discussion.

DETAILED DESCRIPTION

In general, the present invention is directed to an implantablemicro-miniature electronic device, and method of manufacture, with anexternal electrical contact surface, that has excellent hermeticproperties.

An exemplary embodiment of an implantable microelectronic device 10 ofthe present invention is depicted in the simplified, cross-sectionalview of FIG. 1. A silicon integrated circuit chip (“IC”) 20 comprises atop electrically insulating (passivation) layer 30 and an electricalcontact pad 40 which extends through layer 30 to the surface of IC 20.While the exemplary embodiment of the invention is described inconjunction with IC 20, the invention is also useful with other types ofmicroelectronic devices, whether or not they are fabricated on silicon,which require a hermetic electrical connection. Therefore, the presentinvention should not be viewed as restricted to use with IC chips.

While only one contact pad 40 is shown in FIG. 1, those skilled in theart will appreciate that an IC typically has a large number of suchpads. Contact pad 40 is made of copper, aluminum or aluminum alloy inaccordance with standard silicon IC designs and fabrication techniques.As noted, such materials are not biocompatible and so it is necessary tohermetically isolate them. Thus, in accordance with the presentinvention, overlying IC contact pad 40 are multiple layers of metals, orother conductive materials, with suitable hermetic and biocompatibleproperties. In the exemplary embodiment depicted in FIG. 1, there aretwo patterned layers of, preferably, platinum 50 a, 50 b, formed on topof two patterned layers of, preferably, titanium 60 a, 60 b.Alternatively, the patterned layers may be made of iridium, palladium,niobium, titanium nitride or other biocompatible metals or metal alloys.While two layers of titanium and two layers of platinum are shown, anysuitable number of layers of these, or other similar hermetic conductorsmay be used, as described in greater detail below. The upper surface 55of the uppermost conductive layer, i.e., platinum layer 50 a, serves asan electrical contact pad for device 10. The entire device is encased ina biocompatible electrically insulating material 70, such as alumina,which hermetically and electrically isolates IC chip 20. An aperture 80is formed through the surrounding alumina 70 to provide access to uppercontact surface 55, thereby enabling electrical connection with thedevice.

A feature of the present invention is that layer 60 b is larger thancontact pad 40 in its lateral dimensions. Thus, for example, if contactpad 40 is circular with a radius r, then layers 60 b may be dimensionedto have a radius R, where R>r. Alternatively, if contact pad 40 is asquare with a side dimension a, then layer 60 b may have a sidedimension A, where A>a. It is not necessary that layer 60 b have thesame shape as contact pad 40. Thus, pad 40 may be square, while layer 60b is circular. What is important, according to a feature of the presentinvention, is that layer 60 b extends beyond the edge of pad 40 in everydirection. As described in greater detail below, this provides betterhermetic isolation of pad 40 and compensates for any small maskmisalignments during fabrication.

A process for fabricating exemplary device 10 is now described inconnection with FIGS. 2A and 2B. The fabrication and design of IC chip20, or other device used with the present invention, is not consideredpart of the invention and, therefore, will not be described. Multiplelayers 60 a, 60 b, of titanium are formed on top of IC contact pad 40.As described above, while two layers are shown, any suitable number oflayers may be used. In some applications a single layer of titanium maybe sufficient. It will be appreciated that each additional layer addsexpense and processing time. On the other hand, use of more than onelayer improves hermetic properties.

According to the present invention at least the first titanium layer,and preferably all of the titanium layers, overlying pad 40 are largerin areal extent than pad 40, such that they extend beyond the entireedge of pad 40. As described above, this compensates for any inaccuracyin alignment and ensures that the surface of pad 40 is completelycovered. Since a portion of the bottom titanium layer 60 b is depositedon IC insulation layer 30, the insulation layer can be pretreated topromote adhesion with the titanium. Methods of pretreating may includesputtering, RIE, oxygen etch, plasma treatment or combination of two ormore of these methods.

Preferably, one or more mask layers (not shown) formed by standardphotolithography are used to define location of titanium deposition.Preferably, titanium deposition is done using ion beam assisteddeposition (“IBAD”). Specifically, the masked IC substrate is held abovea source of condensing titanium ions, while being simultaneouslybombarded with ions from a plasma, such as argon. Those skilled in theart will appreciate that by carefully controlling the ion beam energy,the current density and the flux of titanium atoms, a dense, relativelydefect free titanium layer can be obtained. The substrate may be rotatedduring the IBAD deposition of titanium to improve the uniformity of thelayer. Additional layers of titanium may be deposited in like manner. Inone method of implementing the present invention, rotation of thesubstrate is reversed with each successive layer.

If titanium is adequate for the application of implantable device 10,metal deposition could be stopped at this point. However, in accordancewith a preferred embodiment, one or more platinum layers are depositedover the titanium layers. The platinum layers may be deposited usingIBAD, as described above. However, the optimal process parameters, i.e.,ion beam energy, the current density and the flux of atoms will differ.It is preferred, as shown in FIG. 2A, to set the diameter of theplatinum layers 50 a, 50 b to be smaller than the underlying titaniumlayers 60 a, 60 b, so that there is an exposed shoulder or annulus oftitanium 65. Titanium shoulder 65 serves as an adhesion promoter for theoverlying electrically insulating hermetic material. However, use of atitanium shoulder is not necessary, and all of the conductive layersmay, instead, have substantially the same diameter.

A thin sacrificial titanium layer 200 is then preferably deposited ontop of uppermost platinum layer 50 a to protect electrical contactsurface 55 during subsequent processing. The sacrificial titanium layermay be formed in a manner similar to that described for the other metallayers, i.e., using photolithography and IBAD. It is noted that sincesacrificial layer 200 is intended to be temporary, it need not have thesame integrity as the other layers.

As shown in FIG. 2B, after the various titanium and platinum layers aredeposited, the entire device is hermetically encased in an insulatorsuch as alumina. As previously noted, the surrounding alumina 70 may bedeposited using IBAD in a known manner. As is known, deposition of analumina to hermetically encase the device may require iterativeprocessing steps whereby the device is repositioned between depositionsteps such that all surfaces of the device are exposed. While this mightbe considered to constitute multiple layers, for purposes of the presentapplication, these multiple layers are collectively considered to be asingle hermetic layer. While use of alumina is preferred, otherelectrically insulating materials may also be used.

In order to obtain a long-lasting hermetic seal the material selectedfor encasing the device should adhere strongly to the exposed surfaces.Loss of adhesion at the interfaces between the layers due to mechanicalor thermal stresses encountered during processing or thereafter cancreate a leakage pathway that allows fluid to migrate into the device.It is noted that shoulder 65 serves as a barrier against fluid migrationin case there is a loss of adhesion between alumina 70 and platinumlayers 50 a, 50 b. In addition, the fact that titanium layer 60 bextends beyond the edge of IC contact pad 40 further provides a furtherbarrier against fluid migration to the surface of the pad.

Titanium is preferred for use in the present invention because of itsstrongly adhesive properties. In particular, titanium adheres stronglyboth to aluminum or copper pads on an IC, and also to platinum andalumina. Titanium is not only less costly than platinum, but it also hasbetter adherence, particularly in respect to aluminum IC pads. However,in some applications, it may be acceptable to use only platinum.

As depicted in FIG. 2B, hermetic insulator 70 completely encases thedevice. Thereafter, an aperture is formed through the insulator 70 touncover the electrode structure. In one method of making the implantabledevice of the present invention, the aperture is created by laserdrilling. Any remaining portion of sacrificial layer 200 may then beremoved, such as by a suitable etching process, preferably one thatselectively etches titanium. The resulting structure is shown in thepreviously described FIG. 1. If necessary, suitable biocompatible wires(not shown) can then be attached to surface 55, for example, bywirebonding.

Further, as shown in FIG. 3 additional metal 90, preferably platinum,palladium, iridium or alloys thereof may be built up in the aperture 80,to improve contact with neural tissue. This may be accomplished byseveral processes, but preferably by electroplating. While FIG. 3 showsa mushroom shaped electrode it should be noted that the electrode may beflush or concave.

A surface of exposed, non-passivated, aluminum electrode is connected toa current driver. The current passes through this electrode into a humanbody. The exposed surface may be a via, or recording electrode, ratherthan a stimulating electrode. The exposed surface may be sircular. Ametal or a combination of metals, alloys or layers, can be deposited ontop of this surface. It is preferred to first deposit titanium metal ina radius that is larger than the circular aluminum metal so that itoverlaps the native passivation. This ensures that the aluminum iscompletely covered. The titanium deposition is done by IBAD. Thesubstrate is held above the source of condensing titanium atoms whilebeing simultaneously bombarded by ions, typically Ar⁺. The ion beamenergy, the current density, and atom arrival rates are controlledprecisely to ensure that the metal film is growing in as dense manner aspossible. The holder for the substrate is rotating in order to increasedeposition uniformity. A second layer of titanium may be deposited,possibly with holder rotating in the opposite direction. Two or morelayers advance the hermetic film.

A final platinum layer is preferably applied. The titanium interlayerserves two purposes. The titanium allows building up some thickness ofmetal that will assist in hermeticity while consuming less of the moreprecious platinum. The titanium layer promotes the adhesion as theplatinum layer adheres well to titanium but not as well to aluminum. Ifplatinum adheres well to the base metal the adhesion layer, liketitanium is not required.

The platinum metal is deposited in a similar manner although the optimalprocess parameters, like beam energy, current density, and atom arrivalrate will differ. It is preferred to deposit two or more platinum layersin order to further ensure hermeticity. It is preferred but notessential to make the diameter of the platinum electrodes smaller thanthe diameter of the titanium electrodes, such that the titanium has anexposed annulus of material that will serve as an adhesion promoter toany film that may subsequently be deposited. Any number of layers ofhermetic metal may be applied according to this method.

A cap layer of sacrificial metal is preferred. A sacrificial metal canbe applied first if any subsequent processing of the substrate includesa process that could damage the surface of the electrode. This layercould absorb the damage and be subsequently removed, for example byetching, to expose a pristine surface of the desired metal. Titanium canbe evaporated onto platinum surface to a thickness of about ≦5 μm. Thesubsequent exposure to a laser results in melting of the titanium. Theresidual titanium can be removed by an etchant, which removes thetitanium but does not affect the underlying platinum.

Patterning of films deposited under harsh environmental conditions isachieved by ion beam assisted deposition (IBAD), which exposes thesubstrate to high temperature, high vacuum and ion beam bombardment. SeeF. A. Smidt, International Materials Reviews, 35 (1990) 61 and J. K.Hirvonen, Mater. Sci. Rep. 6 (1991) 1.

If a liftoff technique is desired only a few common photoresists survivethat environment. Further a mechanical shadow mask may not be able tomeet the layout design rules. The present disclosure provides a novelapproach was using a polymer, like polyimide as the patterning mask.Other polymers are thermoplastic polyimide (Imidex®, epoxy resin,parylene, silicone, liquid crystalline polymer, or PEEK (Victrex®. Themethod is useful during the integration of stimulation electrodes ontoan ASIC component. The method “Peel Off Lift Off” (P.O.L.O.) patterning,unexpected and surprisingly created high resolution, high aspect ratio,multilayer metal post structures on a silicon ASIC device.

Two methods of patterning are commonly applied in microelectronicprocesses, etchback and liftoff. In the etchback method a blanket layerof material is deposited on the entire substrate surface. Those areas inwhich the deposited material is not desired are then cleared bysubtractive micromachining. The subtractive micromachining step mightrequire photolithography or other masking prior to removal of the excessmaterial by chemical or mechanical means. In the liftoff method apatterned mask is placed on the substrate surface prior to deposition ofthe additional material. The mask layer is then stripped, leaving behindthe new layer only in those regions where its presence is desired.

Integrated neurostimulators can take forms of Si ASIC chips integratedwith Al electrode arrays. To make the electrode array suitable forneural stimulation, the Al electrode has to be covered by otherbiocompatible electrode materials, such as Ti and Pt. Other conductivebiocompatible metals are palladium, gold, or silver. Other conductivebiocompatible materials iridium, iridium oxide or titanium nitride. Theadvantages of this method are: Pt and Ti coverage of Al renders the chipbiocompatibility; the hermeticity provided by the metal stackup layerprevents moisture ingress to the inside of the chip during neuralstimulation; and the outside Pt layer endures well of prolongedstimulation without significant corrosion and degradation.

IBAD deposition of metal Ti and Pt results to be effective in achievingthose advantages. However, IBAD requires such as high temperature andlow pressure. The P.O.L.O. technique provides surprising results byapplying smoother conditions.

The P.O.L.O. process begins on a silicon substrate having a surface of anative oxide or passivation of additive oxide or nitride. Openings inthe surface passivation exist to aluminum bond pads. Onto this substratein wafer form is spun a 5 μm to 15 μm, preferably approximately 8 μmthick film of polyimide precursor, which is subsequently cured intopolyimide. A thin film aluminum mask layer is then sputtered onto thepolyimide surface and patterned using traditional dark fieldphotolithography. The features now present as openings in the aluminumare transferred into the polyimide film using a reactive ion etchsystem. The aluminum bond pads on the underlying silicon substrate actas an excellent etch stop to the subsequent RIE process. The surroundingpassivation material exhibits a high etch rate selectivity, whichresults in only a minimal removal of the material which is exposed toreactant species. The partial etch of the passivation layer may bebeneficial if not overdone since the cleanliness and slight roughnesscreated therein are conductive to stronger bonding between the metaldeposit and the passivation layer.

The exposed wafer surface should be cleaned to remove any RIE residuesbefore additional processing is performed. An ultrasonic cleaning of thewafer in DI water is applied for 3 min. After the desired openings arecreated in the polyimide film, the wafer is placed into an IBAD chamberfor deposition of a 2 μm to 8 μm, preferably about 4 μm layer oftitanium. The original thin film aluminum mask can be left in place orremoved prior to IBAD processing to avoid any possible contamination ofthe deposited metal. When the IBAD titanium process is completed thewafer is removed from the chamber and prepared for lift off. The waferis coated in some cases with a second IBAD film of either 1 μm to 5 μm,preferably about 3 μm platinum or titanium. The polyimide film is peeledfrom the silicon surface taking with it all metal from outside thedesired feature locations by cleaving a sliver of wafer from the backside, and pulling it across the wafer face. The resulting wafer surfaceis smooth and free of residues.

The is repeated on some prototype wafers to permit the patterning of asecond metal layer, of smaller diameter, on top of the first set oftitanium posts. The second film contains either 3 μm platinum and/ortitanium. Parts are fabricated on bare silicon wafers and passivatedwith nitride. Post features are laid out in an area array manner toexplore the basic peel off concept, test IBAD material post adhesion,and determine the feasibility of multilayer processing (without theadditional effort of polyimide planarization). A variety of post gridsare tested to determine minimum pitch limits and process uniformity.This way the chosen combinations are specified. IBAD metal layers up to7 μm thick have been successfully processed and feature sizes down to 20μm to 30 μm, preferably about 25 μm diameter on a 100 μm to 150 μm,preferably about 125 μm pitch are achieved with >99% yield on a 3″sample.

Initial evaluation focused on the yield achieved after peeling off thepolyimide mask film. For all features of 25 μm diameter or greater on apitch of 125 μm or greater yield in excess of 99% was found after visualobservation. Feature spacing proved to be a limiting factor independentof feature diameter, as the polyimide mask layer would tear in caseswere adjacent feature edges were within 50 μm.

The adhesion is qualitatively evaluated using a simplified tape peeltest. No failures are found between the base titanium post and thesubstrate. Between the stacked IBAD metal layers, failure depends on thematerial set. For the titanium on titanium samples, 100% of the postsremain in place after the tape is peeled. For the platinum on titaniumsamples, 90% of the posts remain in place after the tape is peeled.

The results are corroborated by a crude scratch shear test performed oneach post stack. In this test a scalpel blade is manually dragged overthe post stacks in an attempt to induce mechanical failure. For thetitanium on titanium samples the blade cuts through the post while forthe platinum on titanium samples the blade causes the platinum disk toseparate from the underlying titanium.

These results prove that the integrity of interfaces between individuallayers is critical and dependent on materials. In cases of Ti/Tistackups, oxidation of the first Ti layer does not seem to jeopardizethe integrity of Ti/Ti stickups. The oxidation is due to exposure to airafter IBAD deposition and RIE of the PI mask layer for the second Tilayer deposition. However, in cases of Ti/Pt stackups, the bondingbetween the first Ti layer and the second Pt layer is somewhat weakeneddue to the oxidation of the first Ti layer, which compromises theapplication as neural stimulation electrodes. It has been proven that Ptsticks fairly well to Ti when it is not oxidized.

Stimulating electrode sites and basic embedded circuitry are simulatedby test structure foundry wafers containing bond pads. The sametechnique is implemented successfully on these foundry processed waferswithout negatively impacting the performance of embedded transistorelements.

This work is achieved using a crude Mylar™ mask and reflects a lowerlimit of the resolution capabilities. With more accurate glassphotomasks successful processing of features with a minimum dimension of10 μm up to a 75 μm pitch is achieved.

If a multilayer stack of IBAD material is desired, severalconfigurations can be realized. A single polyimide layer can be used topattern several sequential films so long as their total thickness isless than the mask layer thickness. Should this simple columnarstructure be insufficient, the post diameter can be either reduced orenlarged for subsequent films. Alternatively, subsequent films can bedeposited in other wafer locations should that be desired.

The material properties of polyimide make it suitable for use indeposition environments over a wide range of conditions. Temperaturesslightly over 400° C. can be handled for durations of at least an hourand exposure to vacuum in the low millitorr range is possible.

Etched features in the polyimide layer exhibit vertical or slightlyundercut cross sectional profiles due to the mechanism involved in thispatterning technique. The deposited material would otherwise be deformedor even popped off the substrate surface during the mask peeling step.Proper RIE (or laser) parameters ensure the necessary wallcharacteristics. Release layers such as parylene, or fluoropolymer canalso be applied.

FIGS. 1-4 show the sequence of the peel-off, lift-off metal patterningmethod. The polymer is patterned to open regions in the location andshape of the desired material features. The desired material is thendeposited. After deposition, the mask polymer is peeled away from thesubstrate, leaving behind the deposited material in the patternedregions alone.

FIG. 4 is a cross-sectional view of an alternate embodiment of thepresent invention showing the mask deposition. This is the first step ofthe process, the polymer mask deposition. A polymer mask 2 is depositedon a host substrate 1. Examples of polymer deposition methods are spincoating, meniscus coating or lamination.

FIG. 5 is a cross-sectional view of an alternate embodiment of thepresent invention showing the mask patterning. This is the second stepof the process, the polymer mask patterning, yielding a patterned maskpolymer 2. Examples of polymer patterning methods are wet etching(liquid chemicals etc.), or dry etching (plasma, laser, gaseous chemicaletc.).

FIG. 6 is a cross-sectional view of an alternate embodiment of thepresent invention showing the material deposition. This is the thirdstep of the process, the material deposition yielding a depositedmaterial 3. Examples of material deposition methods are PVD (physicalvapor deposition such as evaporation, sputtering etc.), or CVD (chemicalvapor deposition).

FIG. 7 is a cross-sectional view of an alternate embodiment of thepresent invention showing the mask polymer removal. This is the fourthstep of the process, the polymer mask removal. This is a key differencefrom current Lift-Off methods which rely on decomposition (dissolution,etching etc) of the mask layer to remove it from the substrate, yieldinga patterned material 4. The method described herein is also differentfrom shadow masking, since it provides superior resolution, density,alignment and other characteristics.

The advantages of the present method are high temperature compatibility,high vacuum compatibility, chemically resistance, resistance to highenergy particle bombardment, high resolution, high density, and highalignment accuracy.

The process of the present invention is particularly well suited forpatterning of films deposited under harsh environmental conditions suchas high temperature, low vacuum and ion or other species bombardment.One example provided in this invention is the packaging of an array ofintegrated electrodes for neural stimulation on an ASIC device. Stackupsof biocompatible metals were successfully applied by this P.O.L.O.technique to hermetically cover the original Al that came with theintegrated Si ASIC chip, making it biocompatible and therefore humanbody implantable.

The embodiments described above are illustrative of the presentinvention and are not intended to limit the scope of the invention tothe particular embodiments described. Accordingly, while one or moreembodiments of the invention have been illustrated and described, itwill be appreciated that various changes can be made therein withoutdeparting from the spirit or essential characteristics thereof.Accordingly, the disclosures and descriptions herein are not intended tobe limiting of the scope of the invention, which is set forth in thefollowing claims.

1. A microelectronic device, comprising: a microelectronic device havingan electrical contact pad thereon, at least one thin patternedconductive layer formed over said electrical contact pad, the topsurface of said at least one patterned conductive layers defining anexternal electrical contact surface, wherein the first layer of said atleast one patterned conductive layer is in direct contact with saidelectrical contact pad, an electrically insulating material hermeticallysurrounding said microelectronic device, said electrically insulatingmaterial having an aperture wherein said external electrical contactsurface is positioned.
 2. The microelectronics device of claim 1 whereinsaid at least one thin patterned conductive layer and said insulatingmaterial are biocompatible.
 3. The microelectronic device of claim 2wherein said electrically insulating material is a ceramic.
 4. Themicroelectronic device of claim 3 wherein said ceramic is alumina,Zirconia, or aluminum nitride.
 5. The microelectronic device of claim 3wherein said ceramic is alumina.
 6. The microelectronic device of claim3 wherein said electrically insulating material is a metal oxide.
 7. Themicroelectronic device of claim 3 wherein said electrically insulatingmaterial is a polymer.
 8. The microelectronic device of claim 2 whereina first layer of said at least one patterned conductive layer comprisegold, nickel, or chromium.
 9. The microelectronic device of claim 2wherein a first layer of said at least one patterned conductive layercomprise a titanium layer.
 10. The microelectronic device of claim 2wherein a second layer of said at least one patterned conductive layercomprise at least one biocompatible metal.
 11. The microelectronicdevice of claim 2 wherein said at least one patterned conductive layercomprise a platinum layer.
 12. The microelectronic device of claim 7comprising a platinum layer formed over said titanium layer.
 13. Themicroelectronic device of claim 2 wherein said at least one patternedconductive layer comprise at least one platinum layer formed over atleast one titanium layer.
 14. The microelectronic device of claim 1wherein said substrate comprising a microelectronic device is anintegrated circuit chip and said electrical contact pad is aluminum,aluminum alloy, copper or copper alloy.
 15. The microelectronic deviceof claim 1 wherein a first patterned conductive layer is larger in itslateral dimensions than said electrical contact pad, such that saidpatterned conductive layer extends beyond the edge of said contact pad.16. The microelectronic device of claim 15 wherein said first patternedconductive layer is titanium and at least one overlying conductive layeris platinum.
 17. The microelectronic device of claim 15 wherein one ofsaid conductive layers defines a shoulder.
 18. A device, comprising: amicroelectronic device located on a silicon substrate, saidmicroelectronic device having a conductive contact pad surrounded byelectrically insulating material, at least one patterned first metallayer formed on said contact pad and extending beyond the edge of saidcontact pad, at least one patterned second metal layer formed over saidfirst metal layer, said second metal layer having an exposed uppercontact surface, an electrically insulating material layer hermeticallysurrounding said microelectronic device and said patterned layers, saidelectrically insulating material layer having an aperture which exposessaid upper contact surface.
 19. The implantable device of claim 18wherein the first metal layer comprises at least one patterned titaniumlayer.
 20. The implantable device of claim 18 wherein the second layercomprises at least one patterned platinum layer.
 21. The implantabledevice of claim 18 wherein said first layer defines a shoulder.
 22. Amethod of making a device having an electrical contact, comprising thesteps of: providing an electrical device having a contact pad, formingat least one patterned conductive layer over said contact pad, said atleast one conductive layer having a first layer formed on said contactpad and a top electrical contact surface, hermetically encasing theresulting structure in an electrical insulator, forming an aperture insaid electrical insulator to expose said electrical contact surface. 23.The method of claim 22 where said electrical contact surface and saidelectrical insulator are biocompatible.
 24. The method of claim 22wherein said step of hermetically encasing the structure in abiocompatible insulator comprises ion beam assisted deposition of aceramic material.
 25. The method of claim 22 wherein the step of formingat least one patterned conductive layer comprises ion beam assisteddeposition of at least one metal.
 26. The method of claim 22 wherein atleast one of said patterned metal layers is titanium or titanium alloy.27. The method of claim 22 wherein at least one of said patterned metallayers is platinum or platinum alloy.
 28. The method of claim 22 whereinat least one patterned layer of titanium and at least one patternedlayer of platinum are formed by beam assisted deposition.
 29. The methodof claim 22 wherein said first patterned conductive layer is larger thansaid contact pad such that it extends beyond the edge of said contactpad.
 30. The method of claim 22 wherein the step of forming an aperturecomprises laser machining.
 31. The method of claim 22 further comprisingthe steps of forming a sacrificial layer over said top electricalcontact surface, such that the top electrical contact surface isprotected during subsequent processing and, thereafter, removing saidsacrificial layer.
 32. The method of claim 22 wherein one of saidconductive layers defines a shoulder.
 33. The method of claim 22 furthercomprising filling said aperture with metal.